ADHSC=0, MUXSEL=0, ADLSTS=00, ADACKEN=0
Configuration register 2
ADLSTS | Long sample time select 0 (00): Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). 1 (01): 12 extra ADCK cycles; 16 ADCK cycles total sample time. 2 (10): 6 extra ADCK cycles; 10 ADCK cycles total sample time. 3 (11): 2 extra ADCK cycles; 6 ADCK cycles total sample time. |
ADHSC | High speed configuration 0 (0): Normal conversion sequence selected. 1 (1): High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). |
ADACKEN | Asynchronous clock output enable 0 (0): Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. 1 (1): Asynchronous clock and clock output enabled regardless of the state of the ADC. |
MUXSEL | ADC Mux select 0 (0): ADxxa channels are selected. 1 (1): ADxxb channels are selected. |